Telecommunication networks transport and switch traffic according to time division multiplexed (TDM) protocols and synchronous optical network (SONET) protocols. It is common for traffic processed by a network switch to be a combination of TDM traffic (e.g., SONET, SDH), which use different formats and timing. SONET traffic can be switched at various levels based on the granularity required by the traffic. The lower levels of granularity include the virtual tributary (VT) level (e.g., VT1.5, VT2, VT3, VT6) and the STS-1 level. One STS-1 carries multiple VT traffic streams. Timing requirements for VT level traffic and STS level traffic are well known in the art.
There are two traditional approaches to designing a VT-level switch. The first approach is to design each line card with full VT processing functionality, which is conceptually illustrated in FIG. 1. Line cards 100 and 150 send and receive SONET signals, for example, OC-1 formatted signals. Optical signals (e.g., OC-1) are converted to corresponding electrical signals (e.g., STS-1). Line cards 100 and 150 demap the VT1.5 signals from the incoming STS-1 signal and transmit the VT1.5 signals to VT switch fabric 190 for switching. Line cards 100 and 150 receive VT1.5 signals from VT switch fabric 190 and map multiple VT1.5 signals to outgoing STS-1 signals. The STS-1 signals are converted to OC-1 signals for transmission over a SONET network.
The architecture of FIG. 1 provides 100% VT1.5 grooming. However, few networks require 100% VT1.5 grooming. Service providers rarely require more than 40% VT1.5 grooming and often require less than 25% VT1.5 grooming. Therefore, the architecture of FIG. 1 is inefficient.
A second approach to providing VT-level switching is to provide a central VT switching resource, which is conceptually illustrated in FIG. 2. Line cards 200 and 250 send and receive data according to SONET protocols. Line cards 200 and 250 provide signals to STS-1 switch fabric 275 at the STS-1 level. If VT-level switching is required, the STS-1 level signals to be switched are sent to VT switch 290, where VT level demapping and switching are performed. After the VT-level switching is performed, the VT signals are mapped to STS-1 signals that are sent to STS-1 switch fabric 275 to be sent to a destination line card.
The architecture of FIG. 2 is a blocking architecture unless VT switch 290 provides 100% VT switching. Blocking architectures may not provide the desired level of switching performance. For example, if VT switch 290 is capable of switching 100 VT signals and more than 100 VT signals are to be switched, the signals in excess of 100 are blocked. If a second VT switch is coupled with STS-1 switch fabric 275, the second VT switch will switch a second group of VT signals. That is, multiple VT switches are mutually exclusive so, while the overall bandwidth to switch all VT signals may be provided, the architecture may be a blocking architecture and not provide the desired functionality.
If VT switch 290 provides 100% VT switching, the cost of a switch according to the architecture of FIG. 2 is comparable to the cost of a switch according to the architecture of FIG. 1. Also, the capacity of (a 100% VT switching) VT switch 290 may not be used efficiently. Thus, neither the architecture of FIG. 1 nor the architecture of FIG. 2 provide efficient VT-level switching.